Hardware functional obfuscation with ferroelectric active interconnects

Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-complexity with significant area, energy, and delay penalty. In this paper, we propose an efficient hardware encryption technique with minimal complexity and overheads based on ferroelectric field-effect transistor (FeFET) active interconnects. By utilizing the threshold voltage programmability of the FeFETs, run-time reconfigurable inverter-buffer logic, utilizing two FeFETs and an inverter, is enabled. Judicious placement of the proposed logic makes it act as a hardware encryption key and enable encoding and decoding of the functional output without affecting the critical path timing delay. Additionally, a peripheral programming scheme for reconfigurable logic by reusing the existing scan chain logic is proposed, obviating the need for specialized programming logic and circuitry for keybit distribution. Our analysis shows an average encryption probability of 97.43% with an increase of 2.24%/ 3.67% delay for the most critical path/ sum of 100 critical paths delay for ISCAS85 benchmarks.

The paper entitled "Hardware Functional Obfuscation with Ferroelectric Active Interconnects" by T. Yu et al. proposed an efficient hardware encryption technique with minimal complexity and overheads based on ferroelectric field-effect transistor (FeFET) active interconnects. The result looks interesting. However, there are several points to be addressed. 1. The FeFET device architecture in this paper is reported in ref. 40 (IEDM, 2016, 11-15) and most of the device performances are clearly presented. Moreover, Ref. 19 (IEEE Transactions on Electron Devices 2021, 68, 516-522) has also expanded the application of the FeFET in security circuit. So the authors should clearly address the novelty of such work.
The authors would like to thank the reviewers and editors for their constructive comments and suggestions that can significantly improve our paper. We have addressed all the comments and made all the necessary modifications to the manuscript. Detailed point-to-point response is as follows.

Review question 1.1
As shown in Figure 2g and i, in logic mode, there are continuous voltages applied on CNTL1 and CNTL2, will it dramatically increase power consumption? The authors should also provide an energy comparison against other camouflage logic designs.
The power consumed by the reconfigurable block is not significantly different from normal logic gates. Figure R1 shows the measured DC I D -V G and I G -V G on a FeFET with W/L=500nm/500nm.
Even though a voltage is continuously applied on CNTL1 and CNTL2, but they are applied only

Review question 1.2
What is the stability of the non-volatile FeFETs? Is there drift present? How does the programmed device behave after a long duration?
Thanks for the reviewer for bringing this up. We have added the retention measurement on a FeFET with W/L=500nm/500nm at different temperatures, as shown in Figure R2. It shows that at room temperature, extracted memory window up to 0.6 V can be retained even after 10 years, demonstrating good stability of the configured states. At higher temperatures, such as 85 • C, the memory window is reduced to 0.1 V after 10 years. Two aspects are worth noticing. First, the presented retention data is by no means the limit of FeFET devices. Better retention in FeFETs have been reported in literature 1, 2 . Therefore, the presented data should not be regarded as the limit of FeFET technologies and can be further improved. Second, for the proposed camouflaging application, the required retention is much relaxed compared with the conventional nonvolatile memory, where occasional reprogramming (e.g., after months or years) can be performed. Figure R2 is added Figure S4(a) in the supplementary. Discussion on FeFET state stability is added on page 18.

Review question 1.3
The authors claim that for c5315CP, encryption gates added in the path lead to double inversions in some cases, which in turn decreases the encryption probability. Could the author give a more detailed explanation?
For C5315CP, we conducted the experiment by adding multiple active interconnect based encryption blocks to the same input to output path. We chose to do so for analysing the impact on timing and encryption probability in such paths. We define double inversion as two times negation of data in the input-output path. Adding more than one encryption blocks(programmed in the inverter mode) to the same input-output path may lead to double inversion of data in the path for some combination of inputs. To demonstrate the logic impact of double inversion on final output we choose an input-output path with two encryption blocks. The screenshot of the timing report of the chosen input-output path with two encryption units is shown in Figure. Figure. R3c shows the circuit after inserting two encryption unit (both programmed to be inverters). We observe that for a set of specific inputs, the intermediate output O inter is "1" as shown in Figure. R3a. After inserting a single encryption unit, O inter value is switched to "0" This implies that more than one encryption units in path may leave the original output unchanged in certain conditions decreasing the encryption probability. Figure R4 is added as Figure S8 and Figure R3 is added Figure S9 in the supplementary.
Relevant texts are added into the last paragraph on page 22.

Review question 1.4
The authors state that "the proposed encryption circuit with the same input results in two different logical outputs based on the programmed states of FeFETs, making it a strong candidate for reverse engineering resilient hardware", Could the author give the experimental results of its immune reverse engineering?
For reverse engineering, hackers tried to extract circuit netlist (functional information) from physical layout. IC reverse engineering involves steps such as depackaging, delayering, high resolution imaging and annotation for extracting gate level netlists 3 . To prevent reverse engineering, any camouflaging technique needs to meet two conditions 3 such as resiliency to reverse engineering and corrupted outputs. Resiliency to reverse engineering indicates that an attacker will not be able to discern the functionality of the camouflaged gates. Corrupted output indicates outputs of the original netlist and deceived netlist are different. In our proposed technique both these con-ditions are met. Our experimental results shows that the same circuit ( Fig.2(j) from the paper) produces both the inverted (Fig.2(m) )and non inverted output (Fig.2(l)). Note we apply the same input voltages (both Input and Eval terminals in Fig. 2j) and the circuit gives two different outputs depending on the previously programmed(configured to either HVT or to LVT) state. This ensures that, the attacker will not be able to identify the functionality of the gate just by inspecting the physical layout. Note, the programming (configuring to LVT/HVT) is also done by just by applying voltages at the Config/Eval( in Fig. 2j)  The authors thank the reviewer for pointing this out. Indeed charge trapping is a serious concern for HfO 2 based FeFET. It is known that charge trapping has an opposite effect on the FeFET compared with polarization switching, reducing the memory window [4][5][6] To minimize the impact of charge trapping induced by write pulses on the FeFET operation, we insert a 0.1s delay between the memory read and memory write such that trapped carriers can be released during the delay. In this way, the charge trapping impact on the FeFET characteristics can be minimized.
Relevant discussions are added into the first paragraph of Section "Verification of the Reconfigurable Block" on page 12.

Review question 2.3
To operate the FeFET device, one typical process is to drive the device with a definite gate voltage after program the device with the same gate terminal. If opposite voltage polarity is used (for example, the device is programmed with -4 V and operates with gate voltage of 1 V), how to ensure the stability of the polarization of the charges in the ferroelectric dielectric? Are there any data to support such results?
We have measured the stability of FeFET reset state, i.e., after -4 V write, when subjecting to 1 V stress during retention, as shown in Figure R5.